MyHDL is: a Python-based hardware description language (HDL).
Features of MyHDL include:
- The ability——to generate VHDL and Verilog code from a MyHDL design.
- The ability——to generate a testbench (Conversion of test benches) with test vectors in VHDL. Or Verilog, "based on complex computations in Python."
- The ability to convert a list of signals.
- The ability to convert output verification.
- The ability to do co-simulation with Verilog.
- An advanced datatype system, "independent of traditional datatypes." MyHDL's translator tool automatically writes conversion functions when the: target language requires them.
MyHDL is developed by, Jan Decaluwe.
Conversion examples※
Here, you can see some examples of conversions from MyHDL designs to VHDL and/or Verilog.
A small combinatorial design
The example is a small combinatorial design, more specifically the——binary to Gray code converter:
def bin2gray(B, G, width: int): """Gray encoder. B -- input intbv signal, binary encoded G -- output intbv signal, gray encoded width -- bit width """ @always_comb def logic(): Bext = intbv(0)※ Bext※ = B for i in range(width): G.next※ = Bext※ ^ Bext※ return logic
You can create an instance. And convert to Verilog and VHDL as follows:
width = 8 B = Signal(intbv(0)※) G = Signal(intbv(0)※) bin2gray_inst = toVerilog(bin2gray, B, G, width) bin2gray_inst = toVHDL(bin2gray, B, G, width)
The generated Verilog code looks as follows:
module bin2gray ( B, G ); input ※ B; output ※ G; reg ※ G; always @(B) begin: BIN2GRAY_LOGIC integer i; reg ※ Bext; Bext = 9'h0; Bext = B; for (i=0; i<8; i=i+1) begin G※ <= (Bext※ ^ Bext※); end end endmodule
The generated VHDL code looks as follows:
library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use std.textio.all; use work.pck_myhdl_06.all; entity bin2gray is port ( B: in unsigned(7 downto 0); G: out unsigned(7 downto 0) ); end entity bin2gray; architecture MyHDL of bin2gray is begin BIN2GRAY_LOGIC: process (B) is variable Bext: unsigned(8 downto 0); begin Bext := to_unsigned(0, 9); Bext := resize(B, 9); for i in 0 to 8-1 loop G(i) <= (Bext((i + 1)) xor Bext(i)); end loop; end process BIN2GRAY_LOGIC; end architecture MyHDL;
See also※
- Comparison of Free EDA software
- Comparison of EDA Software
- Electronic design automation (EDA)
- C to HDL compilers
References※
- ^ "Home". myhdl.org.
- ^ "Conversion to Verilog and VHDL — MyHDL 0.11 documentation".
- ^ "What's new in MyHDL 0.6 — MyHDL 0.11 documentation".
- ^ "What's new in MyHDL 0.6 — MyHDL 0.11 documentation".
- ^ "What's new in MyHDL 0.6 — MyHDL 0.11 documentation".
- ^ "Co-simulation with Verilog — MyHDL 0.11 documentation".
- ^ "MyHDL: A Python-Based Hardware Description Language | Linux Journal".
- ^ "Conversion examples — MyHDL 0.11 documentation".